Peer-reviewed articles 17,970 +


Title: TRANSACTION-LEVEL DESIGNING OF NEUROMORPHIC PROCESSORS MICROARCHITECTURE
TRANSACTION-LEVEL DESIGNING OF NEUROMORPHIC PROCESSORS MICROARCHITECTURE

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Ivan Lukashov; Alexander Antonov
10.5593/sgem2024/2.1/s07.11
10.5593/sgem2024/2.1
1314-2704
978-619-7603-69-9
English
24
2.1
•    Prof. DSc. Oleksandr Trofymchuk, UKRAINE 
•    Prof. Dr. hab. oec. Baiba Rivza, LATVIA
Informatics
Spiking neural networks (SNNs) is a promising research direction to their ability to imitate certain functions of brain. Hardware acceleration of SNN can offer orders of magnitude increase in performance and power efficiency. However, traditional hardware description languages have a barrier for rapid development and prototyping of custom internal hardware mechanisms that affect hardware construction throughout the entire processor structure. Mainstream high-level design methods also have disadvantages, e.g. poor focus on transaction streams management description in dynamically scheduled pipelined structures. To accelerate development of custom neuromorphic processors, we propose Neuromorphix software library, which implements a flexible, reconfigurable microarchitectural template enabling selection of a set of transactions specific to neuromorphic processors. Neuromorphix is based on the previously developed ActiveCore open-source framework, which provides a hardware-oriented intermediate representation for generation of hardware data types, operations and behavioral logic. Development process is accelerated by automatic generation of hardware structures typical for neuromorphic processors using transaction-level approach. At the same time, Neuromorphix supports the option to integrate user-defined hardware blocks and also enables reuse of high-level hardware mechanisms which allows to achieve fold decrease of entry barrier for a wide range of neuromorphic processors developers.
[1] Vaila R., Chiasson J., Saxena V., Deep Convolutional Spiking Neural Networks for Image Classification, 2019, Available at: https://doi.org/10.48550/arXiv.1903.12272 (accessed 1 June 2024).
[2] Coussy P., Gajski D., Meredith M., Takach A., An Introduction to High-Level Synthesis, IEEE Design & Test of Computers, 2009.
[3] Hoover S., Salman A., Top-Down Transaction-Level Design with TL-Verilog, 2018, Available at: https://doi.org/10.48550/arXiv.1811.01780 (accessed 1 June 2024).
[4] Antonov A., Structured Design of Complex Hardware Microarchitectures Based on Explicit Generic Implementations of Custom Microarchitectural Mechanisms, Electronics 2022, Vol. 11, Issue 7, article 1055, 2022.
[5 ] Davies M., Srinivasa N., Lin T.H., Chinya G., Cao Y., Choday S.H., Dimou G., Joshi P., Imam N., Jain S. and Liao Y., Loihi: A neuromorphic manycore processor with on-chip learning. Ieee Micro, 38(1), pp.82-99, 2018.
[6 ] Frenkel C., Lefebvre M., Legat J. D., and Bol D., A 0.086-mm? 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS, IEEE Transactions on Biomedical Circuits and Systems, vol. 13, no. 1, pp. 145-158, 2019.
[7] Modaresi F., Guthaus M., Eshraghian J.K., Openspike: An openram snn accelerator, IEEE International Symposium on Circuits and Systems (ISCAS) 2023 May 21 (pp. 1-5), 2023.
[8] Ye W., Chen Y., Liu Y., The implementation and optimization of neuromorphic hardware for supporting spiking neural networks with MLP and CNN topologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2022 May 30;42(2):448-61, 2022.
The work has been done in Software Engineering and Computers Systems Faculty of ITMO University, Saint-Petersburg, Russian Federation, and has been supported by Russian Science Foundation, grant № 22-11-00145.
conference
https://doi.org/10.5593/sgem2024/2.1/s07.11
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Proceedings of 24th International Multidisciplinary Scientific GeoConference SGEM 2024
24th International Multidisciplinary Scientific GeoConference SGEM 2024, 1 - 7 July, 2024
Proceedings Paper
STEF92 Technology
International Multidisciplinary Scientific GeoConference Surveying Geology and Mining Ecology Management, SGEM
SWS Scholarly Society; Acad Sci Czech Republ; Latvian Acad Sci; Polish Acad Sci; Russian Acad Sci; Serbian Acad Sci and Arts; Natl Acad Sci Ukraine; Natl Acad Sci Armenia; Sci Council Japan; European Acad Sci, Arts and Letters; Acad Fine Arts Zagreb Croatia; Croatian Acad Sci and Arts; Acad Sci Moldova; Montenegrin Acad Sci and Arts; Georgian Acad Sci; Acad Fine Arts and Design Bratislava; Russian Acad Arts; Turkish Acad Sci.
81-88
1 - 7 July, 2024
website
9923
neuromorphic processor, transaction-level designing, spiking neural network, HLS

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