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HARDWARE VIOLATION MONITOR OF TRANSACTION LEVEL REAL-TIME CONSTRAINTS FOR RELIABLE SYSTEMS ON A CHIP
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Asadi N., Saadatmand M., Sjodin M. Run-Time Monitoring of Timing Constraints : A Survey of Methods and Tools, ICSEA 2013: The Eighth International Conference on Software Engineering Advances, pp. 391-401, 2013.
Boule M., Chenard J., Zilic Z. Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug, Computer Design, ICCD 2006, International Conference on, Canada, pp. 294-299, 2007.
Boule M., Chenard J., Zilic Z. Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis, Quality Electronic Design, ISQED '07 8th International Symposium on, Canada, pp. 613-620, 2007.
Shobaki M. On-Chip Monitoring of Single- and Multiprocessor Hardware Real- Time Operating Systems, In 8th International Conference on Real-Time Computing Systems and Applications. IEEE, 2002.
Ciordas C., Basten T., Radulescu A., Goossens K., Meerbergen J. An event-based network-on-chip monitoring service, High-Level Design Validation and Test Workshop, Ninth IEEE International, Netherlands, pp. 149-154, 2004.
Tsai J.J.-P., Fang K.-Y., Horng-Yuan Chen. A noninvasive architecture to monitor real-time distributed systems, Computer, USA, vol. 23, no. 3, pp.11-23, 1990.
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