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HYBRID NISC / TTA HIGH-LEVEL SYNTHESIS TOOL
Abstract
In the article, the authors provide the analysis of the industry state in the field of software and hardware development on the FPGA basis. The primary emphasis is on high-level synthesis (HLS) tools, which allows making a custom design by a non-RTL engineer. The key factors limiting the extensive introduction of HLS in the industry are determined: in most cases is not allowing to get a good solution without an understanding of target microarchitecture and synthesis method; too complicated and unpredictable tool behaviour; limitations on custom IP-block. Authors provide a project of the HLS tool, which based on the hybrid of No Instruction Set Computing (NISC) and Transport Triggered Architecture (TTA), original design flow and synthesis approach. The methodology kernel of that project based on the principles of model-oriented engineering, hardware and software CoDesign and HLS. The application area is a real-time high-frequency control algorithm, hardware-in-the-loop simulation, rapid-prototyping and process-in-the-loop. The distinctive features from the different HLS tools are: ? transparency of a synthesis process, which allows to control over synthesis process manually and to determine and fix non-optimal synthesis decision; ? transparency of a target system process by a data flow style representation; ? deep reconfigurability, which allows a user to make custom IP-blocks with complex behaviour (multifunctional, multitasking, inner resources allocations); ? the ability to reuse the hardware component, which allows to significantly reduce development cycle and custom optimisation for the specific target platform and application domain. In the article, authors describe key project solutions: strengths and weakness of the microarchitecture and approaches to work around; multilevel organisation of provided HLS tools.
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References12
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