SWS Academic Research eLibraryEarth & Planetary Sciences

Scholarly record

USING SELECTIVE MEMORY PERFORMANCE EVALUATION FOR TIME-CRITICAL EMBEDDED SYSTEMS DESIGN

Kustarev, Pavel, Antonov, Alexander, Pinkevich, Vasiliy, Yanalov, Roman

First published: 2015https://doi.org/10.5593/sgem2015/b21/s7.051View metrics

Publication Impact Profile

PlumX
  • Captures
  • Mendeley - Readers: 4
PLUMX see details

Publication details

Title
USING SELECTIVE MEMORY PERFORMANCE EVALUATION FOR TIME-CRITICAL EMBEDDED SYSTEMS DESIGN
Authors
Kustarev, Pavel, Antonov, Alexander, Pinkevich, Vasiliy, Yanalov, Roman
Proceedings
SGEM International Multidisciplinary Scientific GeoConference EXPO Proceedings; 15th International Multidisciplinary Scientific GeoConference SGEM2015, INFORMATICS, GEOINFORMATICS AND REMOTE SENSING
Publisher
Stef92 Technology
Year
2015
Pages
407-414
ISSN
1314-2704
ISBN
978-619-7105-34-6
Language
en
Publication type
Conference Paper
References26

  1. N. Srivastava, V. Pandey, R. Pathak, A. Pandey. Multicore: Move to the Future. International Journal of Engineering Trends and Technology. Vol. 4 , Issue2. 2013.

  2. L. Eeckhout. Computer Architecture Performance Evaluation Methods. Synth. Lect. Comput. Archit. 2010. Vol. 5, № 1. P. 1–145.

  3. J. L. Hennessy, D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, 1990

  4. K. Yotov. On the Role of Search in Generating High Performance BLAS Libraries. 2006. P. 1-211.

  5. K. Yotov, K. Pingali, P. Stodghill. Automatic measurement of memory hierarchy parameters. Proc. 2005 ACM SIGMETRICS Int. Conf. Meas. Model. Comput. Syst. - SIGMETRICS ’05. New York, New York, USA: ACM Press, 2005. P. 181.

  6. K. Yotov, K. Pingali, P. Stodghill. Automatic Measurement of Hardware Parameters for Embedded Processors. 2005. P. 1-10.

  7. LMbench - Tools for Performance Analysis [Online]. URL: http://www.bitmover.com/lmbench/lmbench.html.

  8. Measuring Cache and Memory Latency and CPU to Memory Bandwidth for Use with Intel Architecture - Intel White Paper. 2008. P. 1– 14.

  9. D. Molka et al. Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. 2009 18th Int. Conf. Parallel Archit. Compil. Tech. Ieee, 2009. P. 261–270.

  10. D. Molka et al. Main Memory and Cache Performance of Intel Sandy Bridge and AMD Bulldozer Memory size. MSPC 2014. 2014.

  11. A. Zhai. et al. Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking. 2014. Vol. 11, № 4.

  12. P. Kustarev, S. Bikovsky, A. Antonov, R. Yanalov. Process control and synchronization patterns for SOC. 14th International Multidisciplinary Scientific Geoconference SGEM 2014. GeoConference on Informatics, Geoinformatics and Remote Sensing. Conference Proceedings - 2014, pp. 287-294

  13. Platforma XDSP (rus. «Платформа XDSP») [Online]. URL: http://soc.ifmo.ru/projects/xdsp/ International Multidisciplinary Scientific GeoConfenferences SGEM 2015 www.sgem.org

  14. N. Srivastava, V. Pandey, R. Pathak, A. Pandey. Multicore: Move to the Future. International Journal of Engineering Trends and Technology. Vol. 4 , Issue2. 2013.

  15. L. Eeckhout. Computer Architecture Performance Evaluation Methods. Synth. Lect. Comput. Archit. 2010. Vol. 5, № 1. P. 1–145.

  16. J. L. Hennessy, D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, 1990

  17. K. Yotov. On the Role of Search in Generating High Performance BLAS Libraries. 2006. P. 1-211.

  18. K. Yotov, K. Pingali, P. Stodghill. Automatic measurement of memory hierarchy parameters. Proc. 2005 ACM SIGMETRICS Int. Conf. Meas. Model. Comput. Syst. - SIGMETRICS ’05. New York, New York, USA: ACM Press, 2005. P. 181.

  19. K. Yotov, K. Pingali, P. Stodghill. Automatic Measurement of Hardware Parameters for Embedded Processors. 2005. P. 1-10.

  20. LMbench - Tools for Performance Analysis [Online]. URL: http://www.bitmover.com/lmbench/lmbench.html.

  21. Measuring Cache and Memory Latency and CPU to Memory Bandwidth for Use with Intel Architecture - Intel White Paper. 2008. P. 1– 14.

  22. D. Molka et al. Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. 2009 18th Int. Conf. Parallel Archit. Compil. Tech. Ieee, 2009. P. 261–270.

  23. D. Molka et al. Main Memory and Cache Performance of Intel Sandy Bridge and AMD Bulldozer Memory size. MSPC 2014. 2014.

  24. A. Zhai. et al. Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking. 2014. Vol. 11, № 4.

  25. P. Kustarev, S. Bikovsky, A. Antonov, R. Yanalov. Process control and synchronization patterns for SOC. 14th International Multidisciplinary Scientific Geoconference SGEM 2014. GeoConference on Informatics, Geoinformatics and Remote Sensing. Conference Proceedings - 2014, pp. 287-294

  26. Platforma XDSP (rus. «Платформа XDSP») [Online]. URL: http://soc.ifmo.ru/projects/xdsp/ International Multidisciplinary Scientific GeoConfenferences SGEM 2015 www.sgem.org

View or Download full articleAccess options
Full paper accessChoose SWS login, librarian support, or instant article download.

SWS access login

Login as SWS Scientific Committee

Authors and approved SWS contributors will read and export their own linked papers after identity matching by SWS profile, email and SGEM GlobalID.

For librarian assistance: [email protected]

Purchase Instant Access

48-hour online accessComing soon
Online-only accessComing soon
Download the full article in PDF formatEUR 35
  • Article can be downloaded after successful payment.
  • Article may be used according to SWS library access terms.
  • Article cannot be redistributed.
Get full paper

Back to publication list