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HARDWARE COMPUTATIONAL UNITS DESIGN WITH COMBINED DEBUG CAPABILITIES
Abstract
The article deals with the problem of debug of hardware computational units intended for stream data processing on FPGA. Modern solutions are usually oriented to debug of a hardware unit implementation in a simulator with some model input data or to observing the implemented design in the prototype with real target system environment. However effective analysis and debug of implemented computational algorithms requires combined debug with test data exchange between hardware unit model in simulator and its implementation in system. The proposed approach to hardware units design is based on specific design requirements and design representations such as a high-level algorithm model of hardware units (MATLAB, Python, ?++ languages), their synthesizable descriptions in a register transfer level language пїЅ VHDL or Verilog and their in-system implementations. The reusable components for debug infrastructure realization in FPGA are proposed. The approach allows carrying out the verification of hardware unit implementation and controlling the adequacy of implemented algorithms with different test data sets. The approach is intended to use with the existing register transfer level design flows and CAD tools for FPGA target platform.
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Number of times cited according to Crossref: 1
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