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METHODS OF COMPUTATIONAL PROCESS SCHEDULING FOR SYNTHESIS OF HARDWARE MICROARCHITECTURE

Alexander Antonov

Abstract

Approbation of software design technique in hardware field nowadays is an obvious trend. However, hardware cores with complex microarchitecture are not sufficiently supported by modern design tools. This happens because of remaining focus on structural design rather than designing abstract mechanisms of micro-operations scheduling inside the hardware and their explicit mapping on EDA components. In the article, original formulation of gap between the needed and currently available hardware design methods and tools is proposed. This formulation is based on analogy between complex software environments and hardware microarchitectures, and postulates necessity to codify complex microarchitectural templates in the form of special programmable intermediate representations. These intermediate representations reflect key features of programmable software platforms: support of behavioral description of application functionality within custom computational model, custom API for interaction with system functions and services, behavioral specification of system functions/services implementation. The presented gap is envisioned to overcome by implementation of EDA framework based on ?micro-language? IP (MLIP) cores which is currently in development by the authors. MLIP core is a custom reusable component that implements software-directed synthesis of behavioral specifications of hardware and their translation to target hardware into either representation of other MLIP core or in standard hardware description languages according to specific microarchitectural template. New method of mapping of scheduling mechanisms on programmable templates is proposed. This method assists in implementation of custom abstract microarchitectural mechanisms in the form of new EDA software components based on the class library available in the experimental framework. Experimental designing of educational RISC-V processor core using the proposed microarchitecture description methodology shows dramatic decrease of design time for hardware blocks with complex microarchitecture.

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DOI resolver: doi.org/10.5593/sgem2019/2.1/s07.058

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