Scholarly record
METHODS OF COMPUTATIONAL PROCESS SCHEDULING FOR SYNTHESIS OF HARDWARE MICROARCHITECTURE
Abstract
Approbation of software design technique in hardware field nowadays is an obvious trend. However, hardware cores with complex microarchitecture are not sufficiently supported by modern design tools. This happens because of remaining focus on structural design rather than designing abstract mechanisms of micro-operations scheduling inside the hardware and their explicit mapping on EDA components. In the article, original formulation of gap between the needed and currently available hardware design methods and tools is proposed. This formulation is based on analogy between complex software environments and hardware microarchitectures, and postulates necessity to codify complex microarchitectural templates in the form of special programmable intermediate representations. These intermediate representations reflect key features of programmable software platforms: support of behavioral description of application functionality within custom computational model, custom API for interaction with system functions and services, behavioral specification of system functions/services implementation. The presented gap is envisioned to overcome by implementation of EDA framework based on ?micro-language? IP (MLIP) cores which is currently in development by the authors. MLIP core is a custom reusable component that implements software-directed synthesis of behavioral specifications of hardware and their translation to target hardware into either representation of other MLIP core or in standard hardware description languages according to specific microarchitectural template. New method of mapping of scheduling mechanisms on programmable templates is proposed. This method assists in implementation of custom abstract microarchitectural mechanisms in the form of new EDA software components based on the class library available in the experimental framework. Experimental designing of educational RISC-V processor core using the proposed microarchitecture description methodology shows dramatic decrease of design time for hardware blocks with complex microarchitecture.
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References10
Nane R. et al, A Survey and Evaluation of FPGA High-Level Synthesis Tools, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, vol. 35/issue 10, pp 1591-1604, 2015;
Canis A. et al. From software to accelerators with LegUp high-level synthesis, 2013 International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES) pp. 1-9 2013.
Shacham O., Horowitz M. Rethinking Digital Design: Why Design Must Change, IEEE MICRO. 2010. Vol. 9. P. 9–24.
Shacham O. Chip Multiprocessor Generator: Automatic Generation of Custom and Heterogeneous Compute Platforms. PhD thesis. May, 2010. [Electronic resource] URL: https://purl.stanford.edu/wv793rg3775 Time of access: 07.03.2019.
Lee Y., Bailey S., Richards B. An Agile Approach to Building RISC-V Microprocessors, IEEE Micro. 2016. P. 8–20.
Antonov A., Kustarev P., Bikovsky S., Improving Microarchitecture Design and Hardware Generation using Micro-Language IP Cores, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS) - 2017, pp. 1-6.
Bachrach J. et al. Chisel: Constructing Hardware in a Scala Embedded Language, The 49th Annual Design Automation Conference 2012, DAC ’12, San Francisco, CA, USA, June 3-7. 2012. P. 1216–1225.
Izraelevitz A. et al. Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations, IEEE/ACM Int. Conf. Comput. Des. Dig. Tech. Pap. ICCAD. 2017. Vol. 2017–Novem. P. 209–216.
Bachrach J., et al, Chisel: Constructing Hardware in a Scala Embedded Language, 49th ACM/EDAC/IEEE Design Automation Conference (DAC), IEEE, 2012;
Greaves D.J., Layering RTL, SAFL, Handel-C and Bluespec Constructs on Chisel HCL, ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), IEEE, 2015. P. 108–117.
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