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TRANSACTION-LEVEL DESIGNING OF NEUROMORPHIC PROCESSORS MICROARCHITECTURE
Abstract
Spiking neural networks (SNNs) is a promising research direction to their ability to imitate certain functions of brain. Hardware acceleration of SNN can offer orders of magnitude increase in performance and power efficiency. However, traditional hardware description languages have a barrier for rapid development and prototyping of custom internal hardware mechanisms that affect hardware construction throughout the entire processor structure. Mainstream high-level design methods also have disadvantages, e.g. poor focus on transaction streams management description in dynamically scheduled pipelined structures. To accelerate development of custom neuromorphic processors, we propose Neuromorphix software library, which implements a flexible, reconfigurable microarchitectural template enabling selection of a set of transactions specific to neuromorphic processors. Neuromorphix is based on the previously developed ActiveCore open-source framework, which provides a hardware-oriented intermediate representation for generation of hardware data types, operations and behavioral logic. Development process is accelerated by automatic generation of hardware structures typical for neuromorphic processors using transaction-level approach. At the same time, Neuromorphix supports the option to integrate user-defined hardware blocks and also enables reuse of high-level hardware mechanisms which allows to achieve fold decrease of entry barrier for a wide range of neuromorphic processors developers.
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References4
Vaila R., Chiasson J., Saxena V., Deep Convolutional Spiking Neural Networks for Image Classification, 2019, Available at: DOI: 10.48550/arXiv.1903.12272 (accessed 1 June 2024).
Coussy P., Gajski D., Meredith M., Takach A., An Introduction to High-Level Synthesis, IEEE Design & Test of Computers, 2009. DOI: 10.1109/mdt.2009.69
Hoover S., Salman A., Top-Down Transaction-Level Design with TL-Verilog, 2018, Available at: DOI: 10.48550/arXiv.1811.01780 (accessed 1 June 2024).
Modaresi F., Guthaus M., Eshraghian J.K., Openspike: An openram snn accelerator, IEEE International Symposium on Circuits and Systems (ISCAS) 2023 May 21 (pp. 1-5), 2023. DOI: 10.1109/iscas46773.2023.10182182
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